Controlling leakage power in NanoCMOS SoCs (CLEAN)

Aim of project
Today’s greater than ever functionality of electronic devices is possible only by integrating an increasing number of highly complex tasks into so-called embedded systems on chip (SoC). According to Moore’s Law, the complexity of hardware systems doubles itself exponentially over time. This trend is still continuing, already enabling chips which integrate one billion transistors. The required technology shrinking, now below 65nm, causes the problem of dramatically increasing power consumption, especially as a result of so-called leakage currents. CLEAN is a project, in which the problem of leakage currents in upcoming technologies (65nm and below) is addressed. The main aims of the CLEAN project are:
Analysis and development of design techniques for leakage reduction;
Development of EDA tools for leakage aware design using design techniques;
Development of EDA tools for high level leakage prediction, supporting leakage aware design.

Expected results
Computationally effective methods of estimation of leakage currents, with manufacturing disturbances taken into account;
Methods of reduction of the leakage component in the total power consumption in CMOS VLSI chips.