NANOSIL silicon-based nanostructures and nanodevice for long term nanoelectronics applications
supervisor Prof. Romuald B. Beck, Ph.D., D.Sc.
e-mail r.beck@imio.pw.edu.pl
tel. +48 22 234 75 34
beginning 2008.01.01
end 2010.12.31
Project coordinator
INPG Enterprise S.A. France.
Partners Institut National Polytechnique de Grenoble, France; The University of Warwick, United Kingdom; Rheinisch-Westfaelische Technische Hochschule Aachen, Germany; Kungliga Tekniska Hogskolan, Sweden; Consiglio Nazionale Interunuiversitario per la Nanoelettronica, Italy; Universite Catholique de Louvain, Belgium; Interuniversitair Micro-Electronica Centrum VZW, Belgium; Commisariat a L`Energie Atomiue, France; Stmicroelectronics Crolles 2 SAS, France; Institut Superieur D`Electronique et du Numerique, France; Universite Paris-Sud, France; Gesellschaft Fuer Angewandte Mikro- und Optoelektronik mit Beschrankter Haftung — AMO GmbH, Germany; Forschungszentrum Juelich GmbH, Germany; Qimonda Dresden GmbH & Co.OHG, Germany; Technische Universitaet Braunschweig, Germany; Universitaet Stuttgart, Germany; National Centre for Scientifi c Research Demokritos, Greece, University College Cork — national University of Ireland, Cork, Ireland; Universidad Rovira i Virgili, Spain; Chalmers Tekniska Hoegskola Aktiebolag, Sweden; Ecole Polytechnique Federale de Lausanne, Switzerland; Eidgenoessische Technische Hochschule Zuerich, Switzerland; Synopsys Switzerland LLC, Switzerland; The University og Glasgow, United Kingdom, University of Liverpool, United Kingdom; The University ogf Newcastle Upon Tyne, United Kingdom.
Aim of project
Realization of research for the semiconductor industry targeted at n+4 generation of CMOS integrated circuits and new concepts of device construction and their technology. The consortium members exhibit complementary skills and competences in the fi eld of modeling, technology and diagnostics and characterization of semiconductor devices and integrated circuits.
During the project realization it is planned, among others, to test new gate structure and device channel materials (both nonstrained and strained), Schottky barriers as carrier emitters.
New mathematical-physical models will also be developed of complete devices electrical behavior and of their functional parts, as well as of the evaluation of their electro-physical properties from test structures characteristics.
Adaptation of classical characterization methods and development of novel ones, especially — of electrical characterization methods — is also planned.
Expected results
The obtained knowledge, skills and, above all, results will be transferred to IC manufacturers as a starting point in their individual studies aiming at introduction of new generations of integrated circuits into production.
Polish version